In order to explain the background of the present invention, reference will be first made to FIG. 1 which is a block diagram showing a conventional semiconductor logic integrated circuit device ( hereinafter referred to as an IC device ). In FIG. 1, input buffers (IB.sub.1) to (IB.sub.4) receive input signals in parallel, respectively, which are supplied from an external signal supply unit ( not shown ) to input terminals (I.sub.1) to (I.sub.4), and the parallel outputs of the input buffers (IB.sub.1) to (IB.sub.4) are then applied to a logic unit (LG) to be subjected to logical signal processing. Output signals P.sub.1 to P.sub.4 of the logic unit (LG) are output through output buffers (OB.sub.1) to (OB.sub.4) to output terminals (O.sub.1) to (O.sub.4), respectively. Electric power is supplied to the above described elements through a common power supply terminal and a common power supply line ( not shown ).
To test and evaluate the IC device, the IC device is coupled to a testing device ( hereinafter referred to as a tester ) so that a test pattern signal is applied to the input terminals (I.sub.1) to (I.sub.4), and the logical verification of the IC device is accomplished based on the output logic levels at the output terminals (O.sub.1) to (O.sub.4) in response to the input of the test pattern signal.
With such a conventional IC device as described above, variation in power supply current--which may be caused by variations in the output logic levels of the output buffers (OB.sub.1) to (OB.sub.4)--is relatively larger than that which may be caused by the other circuit elements. Therefore, when a large number of output signals switch their logic levels to either high logic level (H) or low logic level (L) simultaneously the power supply current varies remarkably in response to the switch. This results in variation in power voltage which may be caused by the above described transient variation of the power supply current and a distributed inductance which exists along circuit elements including coupling members for coupling the IC to be tested to the tester, jigs such as a performance board and wiring in the tester.
Since the logic levels of the test pattern signal which is applied to the input terminals (I.sub.1) to (I.sub.4) are determined based on the voltage level of a voltage appearing at a common terminal of the tester, there is a possibility that the variation in the power supply voltage may be superposed on the test pattern signal as noise, resulting in a decrease in the input operation margin of the IC device. In the worst case, this results in an occurrence of errors in the logical operation thereof.
In order to overcome the above described drawbacks, a test pattern signal may be used which does not cause the output levels of the output signals from the IC device to vary simultaneously. In this case, however, such a test pattern signal may not meet the logical processing condition of the IC device to be tested, and therefore is not practical to use for fully testing the IC.
The conventional semiconductor logic integrated circuit device thus constructed is disadvantageous in that, since it is necessary to apply a test pattern signal to the input terminals of the IC device successively in order to determine the logic levels of the output signal therefrom, a relatively long period of time is required to carry out the test operation, and a decrease in the input operation margin may occur due to the variation in the power supply voltage which may be caused by the abrupt and simultaneous variation of the output signal levels in the same potential direction.